Silicon Nanowire Field-Effect Devices as Low-Noise Sensors

  • Date:
  • Location: Polhemsalen, Ångströmlaboratoriet, Lägerhyddsvägen 1, Uppsala
  • Doctoral student: Chen, Xi
  • About the dissertation
  • Organiser: Fasta tillståndets elektronik
  • Contact person: Chen, Xi
  • Disputation

This thesis presents a comprehensive study on design, fabrication, and noise reduction of SiNWFET-based sensors on silicon-on-oxide (SOI) substrate.

In the past decades, silicon nanowire field-effect transistors (SiNWFETs) have been explored for label-free, highly sensitive, and real-time detections of chemical and biological species. The SiNWFETs are anticipated for sensing analyte at ultralow concentrations, even at single-molecule level, owing to their significantly improved charge sensitivity over large-area FETs. In a SiNWFET sensor, a change in electrical potential associated with biomolecular interactions in close proximity to the SiNW gate terminal can effectively control the underlying channel and modulate the drain-to-source current (IDS) of the SiNWFET. A readout signal is therefore generated. This signal is primarily determined by the surface properties of the sensing layer on the gate terminal, with sensitivity close up to the Nernstian limit widely demonstrated. To achieve a high signal-to-noise ratio (SNR), it is essential for the SiNWFETs to possess low noise of which intrinsic device noise is one of the major components. In metal-oxide-semiconductor (MOS)-type FETs, the intrinsic noise mainly results from carrier trapping/detrapping at the gate oxide/semiconductor interface and it is inversely proportional to the device area.

This thesis presents a comprehensive study on design, fabrication, and noise reduction of SiNWFET-based sensors on silicon-on-oxide (SOI) substrate. A novel Schottky junction gated SiNWFET (SJGFET) is designed and experimentally demonstrated for low noise applications. Firstly, a robust process employing photo- and electron-beam mixed-lithography was developed to reliably produce sub-10 nm SiNW structures for SiNWFET fabrication. For a proof-of-concept demonstration, MOS-type SiNWFET sensors were fabricated and applied for multiplexed ion detection using ionophore-doped mixed-matrix membranes as sensing layers. To address the fundamental noise issue of the MOS-type SiNWFETs, SJGFETs were fabricated with a Schottky (PtSi/silicon) junction gate on the top surface of the SiNW channel, replacing the noisy gate oxide/silicon interface in the MOS-type SiNWFETs. The resultant SJGFETs exhibited a close-to-ideal gate coupling efficiency (60 mV/dec) and significantly reduced device noise compared to reference MOS-type SiNWFETs. Further optimization was performed by implementing a three-dimensional Schottky junction gate wrapping both top surface and two sidewalls of the SiNW channel. The tri-gate SJGFETs with optimized geometry exhibited significantly enhanced electrostatic control over the channel, thereby confined IDS in the SiNW bulk, which greatly improved the device noise immunity to the traps at bottom buried oxide/silicon interface. Finally, a lateral bipolar junction transistor (LBJT) was also designed and fabricated on a SOI substrate aiming for immediate sensor current amplification. Integrating SJGFETs with LBJTs is expected to significantly suppress environmental interference and improve the overall SNR especially under low sensor current situations.